Semiconductor chips are commonly connected to other circuitry using solder bumps having a diameter of about 100 microns. These solder joints suffer thermal fatigue failures because of the difference in coefficient of thermal expansion (CTE) between the silicon and the chip carriers to which they are attached. Using the injection molded solder (IMS) technique, solder interconnects can be fabricated on semiconductor chips or chip carriers with controlled shape and composition to increase the fatigue life of the joints. Thus, this invention pertains to improvements of solder interconnections for better electrical performance and/or increased mechanical robustness and the fabrication process of same using IMS.
IMS is a relatively new process with many applications, primarily suited for low-cost solder bumping of semiconductor wafers. In IMS, a scanning head dispenses molten solder through a linear slot in the head over a mold plate to fill cavities therein with molten solder.
After the scan, the solder in the cavities is solidified and then the mold plate is aligned to and placed in contact with a wafer (or die or semiconductor chip) by an appropriate fixture. This assembly is then heated to facilitate reflow and transfer of the solder from the mold plate cavities to metallized pads on the wafer. After cooling and separating the wafer and mold plate, the wafer has been bumped with an array of solder preforms typically used for flip chip applications.
While the technology disclosed in U.S. Pat. No. 6,056,191, assigned to the assignee of the present invention, and entitled “Method and Apparatus for Forming Solder Bumps” represents a major advance in the art, it typically produces spherical solder joints that exhibit several problems. First, the spherical solder joints have limited fatigue life due to a difference in coefficient of thermal expansion between the silicon die and the substrate, often an organic material. To address this CTE mismatch, an additional underfill material is needed between the silicon die and substrate to reduce the mechanical stresses on the solder bumps. As the level of integration in silicon continues to increase, the number and density of solder interconnections also must increase, driving a reduction in size of the spherical solder joints and making it difficult or impossible for underfill to be used. Second, silicon chip sizes are increasing, which also limits the ability of underfills to reinforce conventional spherical solder interconnects. Third, power requirements for silicon devices are increasing, particularly for microprocessor chips; and conventional solder interconnects may not be able to withstand the higher currents needed to supply that power. Finally, as newer interconnect structures are developed such as optical interconnects, the underfill material itself will present a problem, since optical communication between the die and substrate is prevented due to the opaque nature of the material.
The first problem is shown in FIG. 1, wherein a die or chip 20 (typically an integrated circuit silicon chip) is electrically interconnected to a substrate 22 by a series of solder bumps 24, as is well known in the art. The typically small height to width aspect ratio (<1) of standard flip chip bumps makes the solder prone to mechanical stresses, which are greatest at the plane represented by arrows 26, as the chip power and temperature varies over its life. This CTE mismatch caused problem is aggravated as chips get larger and thus the DNP (distance to neutral point) is increased. Without underfill, interconnect failures happen at unacceptably short lifetimes.
FIG. 2 shows, in the regions between the solder bumps 24, an underfill layer 28 applied between the chip 20 and the substrate 22. This mitigates the stresses on the solder bumps themselves, but adds a processing step that is time-consuming and adds cost. As signal and power requirements increase, the smaller spherical size of each bump will not allow sufficient stand-off between the chip and the substrate, which has two deleterious effects. First, the capillary underfill process becomes very slow or impossible; and second, the mechanical stress from CTE mismatch is increased. Additionally, this underfill layer is generally opaque and thus prevents optical communication between the bottom of the chip 20 and the substrate 22, as may be desirable in advanced packaging schemes.